Renesas Electronics ISLA112P50 / ISLA214P50 500MSPS FemtoCharge™ ADCs
Renesas / Intersil ISLA112P50 and ISLA214P50 are 12-bit and 14-bit 500MSPS analog-to-digital converters designed with Intersil's proprietary FemtoCharge™ technology on a standard CMOS process. FemtoCharge is a charge-domain signal processing technology that drastically reduces the power consumption over traditional voltage-domain design techniques. These Renesas / Intersil devices utilize two time-interleaved 250MSPS unit ADCs to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Renesas / Intersil Interleave Engine performs automatic correction of offset, gain, and sample time mismatches between the unit ADCs to optimize performance. An SPI port on these devices allows for extensive configurability of the ADC. The SPI also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands and configure many dynamic parameters. Digital output data is presented in selectable LVDS or CMOS formats.
ISLA112P50/55210EV1Z is an evaluation platform featuring Intersil's ISL55210 high-speed Fully Differential Amplifier and ISLA112P50 High Speed, Low Power 12-bit, 500Msps ADC. The PCB is compatible with Intersil's existing high speed ADC evaluation platform allowing for easy performance measurement and analysis. ISLA214P50-55210EV1Z is an evaluation platform featuring ISL55210 FDA and ISLA214P50 High Speed, High Performance, 14-bit, 500MSPS ADC, the ISLA214P50. This PCB daughterboard mates to Intersil’s existing high speed ADC evaluation platform allowing for easy performance measurement and analysis.
Features
- ISLA112P50 Features
- 1.15GHz Analog Input Bandwidth
- 90fs Clock Jitter
- Automatic Fine Interleave Correction Calibration
- Multiple Chip Time Alignment Support via the Synchronous
- Clock Divider Reset
- Programmable Gain, Offset and Skew Control
- Over-Range Indicator
- Clock Phase Selection
- Nap and Sleep Modes
- Two’s Complement, Gray Code or Binary Data Format
- DDR LVDS-Compatible or LVCMOS Outputs
- Programmable Test Patterns and Internal Temperature Sensor
- ISLA214P50 Features
- Automatic fine interleave correction calibration
- Single supply 1.8V operation
- Clock duty cycle stabilizer
- 75fs clock jitter
- 700MHz bandwidth
- Programmable built-in test patterns
- Multi-ADC support
- SPI programmable fine gain and offset control
- Support for multiple adc synchronization
- Optimized output timing
- Nap and sleep modes
- 200μs sleep wake-up time
- Data output clock
- DDR LVDS-compatible or LVCMOS outputs
- Selectable clock divider
Applications
- ISLA112P50 Applications
- Radar and Electronic/Signal Intelligence
- Broadband Communications
- High-Performance Data Acquisition
- ISLA214P50 Applications
- Radar array processing
- Software defined radios
- Broadband communications
- High-performance data acquisition
- Communications test equipment
ISLA112P50 Block Diagram
ISLA214P50 Block Diagram
Published: 2013-05-21
| Updated: 2022-03-11