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Lattice Semiconductor Mach-NX FPGAs

Lattice Semiconductor Mach-NX Field Programmable Gate Arrays are low-density FPGAs, including enhanced security features and on-chip dual boot flash comprised of SoC and FPGA partitions. The enhanced security features include Advanced Encryption Standard (AES) AES-128/256, Secure Hash Algorithm (SHA) SHA-256/384, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC) HMAC-SHA256/384, Public Key Cryptography, and Unique Secure ID.

Mach-NX FPGAs combine a secure enclave (an advanced, 384-bit hardware-based crypto engine supporting reprogrammable bitstream protection) with a logic cell (LC) and I/O block. The secure enclave helps secure firmware, and the LC and I/O block enables system control functions such as power management and fan control. The components can verify and install over-the-air firmware updates, keeping systems compliant with evolving security guidelines and protocols. The Mach-NX FPGA’s parallel processing architecture and dual-boot flash memory configuration provide the near-instantaneous response times needed to detect and recover from attacks (a level of performance beyond the capabilities of other HRoT platforms like MCUs).

The Lattice Semiconductor Mach-NX devices are a Root of Trust hardware solution that can easily expand to protect the whole system with enhanced bitstream security and user-mode functions. Mach-NX device supports the latest industry-standard I/O and provides breakthrough I/O density with a high number of options for I/O programmability.

Features

  • Up to 8.4K LC of user logic, 2669kbits of user flash memory, and a dual boot flash feature
  • Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC
  • Configuration of PFR and security functions through Lattice Propel simplifies developer experience
  • Highly reliable, low power and 3X better SER performance to comparable CMOS technologies

Applications

  • Secure boot and Root of Trust
  • Compute and storage
  • Wireless communications
  • Industrial control systems

Specifications

  • Solutions
    • Best-in-class control FPGA with advanced security functions, provides secure/authenticated boot and Root of Trust function
    • Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications
    • High I/O devices for I/O expansion applications
  • Flexible architecture with high I/O to LC ratio with up to 379 I/O pins
  • Cryptographic secure enclave
    • Advanced Encryption Standard (AES), AES-128/256 encryption/decryption
    • Secure Hash Algorithm (SHA), SHA-256/384
    • Elliptic Curve Digital Signature Algorithm (ECDSA), ECDSA-based authentication
    • Hash Message Authentication Code (HMAC), HMAC-SHA256
    • Elliptic Curve Integrated Encryption Scheme (ECIES), ECIES encryption and decryption
    • True Random Number Generator (TRNG)
    • Key management using Elliptic Curve Diffie-Hellman (ECDH) public-key cryptography
    • Unique Secure ID
    • Guards against malicious attacks
    • Mailbox interface to SoC function block
    • Federal Information Processing Standard (FIPS) supported security protocols
  • High performance, flexible I/O buffer
    • Programmable sysI/O™ buffer supports a wide range of interfaces on select banks
      • LVCMOS 3.3/2.5/1.8/1.5/1.2
      • LVTTL
      • LVDS, Bus-LVDS, MLVDS, and LVPECL
      • Schmitt trigger inputs, up to 0.5V hysteresis
    • Ideal for I/O bridging applications
    • Slow/Fast slew rate controls
    • I/O support hot socketing
    • On-chip differential termination
    • Programmable pull-up or pull-down mode
  • Pre-engineered source-synchronous I/O
    • DDR registers in I/O cells
    • Dedicated gearing logic
    • Generic DDR, DDRx2, and DDRx4
    Flexible on-chip clocking
    • 5x primary clock inputs
    • 8x internal primary clock lines
    • On-chip oscillator with 5.5% accuracy
    • 2x analog PLLs per device with fractional-n frequency synthesis, wide input frequency range (7MHz to 400MHz)
    • IEEE standard 1149.1 boundary scan
    • IEEE 1532 compliant in-system programming
  • Nonvolatile, reconfigurable
    • Instant-on
    • Multi-sectored UFM for customer data storage
    • Single-chip, secure solution
    • Programmable through JTAG, SPI, or I2C
    • Reconfigurable Flash supports background programming of non-volatile memory
  • TransFR reconfiguration, in-field logic update while I/O holds the system state on select banks
  • SoC function block
    • 32-bit RISC-V processor with on-chip firmware RAM and AHB-Lite master interface
    • Cryptographic Secure Enclave
    • On-chip hardened functions
      • SPI
      • I2C
      • Timer/counter
      • PFR

Block Diagram

Block Diagram - Lattice Semiconductor Mach-NX FPGAs

Additional Resources

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Published: 2020-12-14 | Updated: 2025-10-15