A3R12E30DBF-8E

Zentel Japan
155-A3R12E30DBF-8E
A3R12E30DBF-8E

Mfr.:

Description:
DRAM DDR2 512Mb, 64Mx8, 800 at CL5, 1.8V, FBGA-60

Datasheet:
ECAD Model:
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Learn more about Zentel Japan A3R12E30DBF-8E

In Stock: 63

Stock:
63 Can Ship Immediately
Factory Lead-Time:
16 Weeks Estimated factory production time for quantities greater than shown.
Quantities greater than 63 will be subject to minimum order requirements.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (CAD)

Qty. Unit Price
Ext. Price
$5.05 $5.05
$4.73 $47.30
$4.59 $114.75
$4.48 $224.00
$4.37 $437.00
$4.24 $1,060.00
$4.18 $2,090.00
$4.08 $4,080.00
$3.91 $9,462.20

Product Attribute Attribute Value Select Attribute
Zentel Japan
Product Category: DRAM
RoHS:  
SDRAM - DDR2
512 Mbit
8 bit
400 MHz
FPGA-60
64 M x 8
400 ps
1.7 V
1.9 V
0 C
+ 85 C
DDR2
Tray
Brand: Zentel Japan
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: TW
Moisture Sensitive: Yes
Mounting Style: SMD/SMT
Product Type: DRAM
Factory Pack Quantity: 2420
Subcategory: Memory & Data Storage
Supply Current - Max: 65 mA
Tradename: Zentel Japan
Unit Weight: 159 mg
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Attributes selected: 0

Datasheet

CNHTS:
8542329000
USHTS:
8542320028
ECCN:
EAR99

DDR2 SDRAM

Zentel DDR2 SDRAM features a double-data-rate architecture with two data transfers per clock cycle. The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture. A bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. DQS is edge-aligned with data for READs; center-aligned with data for WRITEs Differential clock inputs (CK and /CK). The DLL aligns DQ and DQS transitions with CK transitions.

FEATURED PRODUCTS
ZENTEL JAPAN

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