LS1020ASN7HNB

NXP Semiconductors
841-LS1020ASN7HNB
LS1020ASN7HNB

Mfr.:

Description:
Microprocessors - MPU Layerscape 32-bit Arm Cortex-A7, Dual-core, 800MHz, 0 to 105C, Security disabled

ECAD Model:
Download the free Library Loader to convert this file for your ECAD Tool. Learn more about ECAD Model.
This product may require additional documentation to export from the United States.

Availability

Stock:
Non-Stocked
Factory Lead-Time:
26 Weeks Estimated factory production time.
Long lead time reported on this product.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (CAD)

Qty. Unit Price
Ext. Price
$97.00 $97.00
$83.92 $839.20
$67.49 $1,687.25

Product Attribute Attribute Value Select Attribute
NXP
Product Category: Microprocessors - MPU
Shipping Restrictions:
 This product may require additional documentation to export from the United States.
RoHS:  
ARM Cortex A7
2 Core
32 bit
800 MHz
FCPBGA-525
32 kB
32 kB
1 V
LS1020A
SMD/SMT
0 C
+ 105 C
Tray
Brand: NXP Semiconductors
Data RAM Size: 128 kB
Instruction Type: Floating Point
Interface Type: Audio, Ethernet, PCI-e, Serial, USB
L2 Cache Instruction / Data Memory: 512 kB
Memory Type: DDR3L / DDR4 SDRAM
Moisture Sensitive: Yes
Number of I/Os: 109 I/O
Number of Timers/Counters: 8 Timer
Processor Series: QorIQ Layerscape LS1020A
Product Type: Microprocessors - MPU
Factory Pack Quantity: 84
Subcategory: Microprocessors - MPU
Tradename: QorIQ
Watchdog Timers: Watchdog Timer
Part # Aliases: 935315866557
Unit Weight: 1 g
Products found:
To show similar products, select at least one checkbox
Select at least one checkbox above to show similar products in this category.
Attributes selected: 0

CAHTS:
8542310000
CNHTS:
8542319091
USHTS:
8542310045
KRHTS:
8542311000
TARIC:
8542319000
MXHTS:
8542310302
ECCN:
3A991.a.1

Layerscape Architecture

NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.